Satish Narayanasamy

Orcid: 0000-0001-5016-1214

Affiliations:
  • University of Michigan, Ann Arbor, USA


According to our database1, Satish Narayanasamy authored at least 72 papers between 2003 and 2023.

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Bibliography

2023
nPoRe: n-polymer realigner for improved pileup-based variant calling.
BMC Bioinform., December, 2023

GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2021
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array.
IEEE J. Solid State Circuits, 2021

DOLMA: Securing Speculation with the Principle of Transient Non-Observability.
Proceedings of the 30th USENIX Security Symposium, 2021

SquiggleFilter: An Accelerator for Portable Virus Detection.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

GenomicsBench: A Benchmark Suite for Genomics.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Sound garbage collection for C using pointer provenance.
Proc. ACM Program. Lang., 2020

17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Relaxed Persist Ordering Using Strand Persistency.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Language Support for Memory Persistency.
IEEE Micro, 2019

Iodine: Fast Dynamic Taint Tracking Using Rollback-free Optimistic Hybrid Analysis.
Proceedings of the 2019 IEEE Symposium on Security and Privacy, 2019

Sensor Training Data Reduction for Autonomous Vehicles.
Proceedings of the 2019 Workshop on Hot Topics in Video Analytics and Intelligent Edges, 2019

Characterization of Unnecessary Computations in Web Applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

InvisiPage: oblivious demand paging for secure enclaves.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Software Wear Management for Persistent Memories.
Proceedings of the 17th USENIX Conference on File and Storage Technologies, 2019

2018
Persistency for synchronization-free regions.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

GenAx: A Genome Sequencing Accelerator.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Optimistic Hybrid Analysis: Accelerating Dynamic Analysis through Predicated Static Analysis.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Language-level persistency.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

InvisiMem: Smart Memory Defenses for Memory Bus Side Channel.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Compute Caches.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

AsyncClock: Scalable Inference of Asynchronous Event Causality.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
DRF<i>x</i>: An Understandable, High Performance, and Flexible Memory Model for Concurrent Languages.
ACM Trans. Program. Lang. Syst., 2016

2015
The Silently Shifting Semicolon.
Proceedings of the 1st Summit on Advances in Programming Languages, 2015

CilkSpec: optimistic concurrency for Cilk.
Proceedings of the International Conference for High Performance Computing, 2015

Efficiently enforcing strong memory ordering in GPUs.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Accelerating asynchronous programs through event sneak peek.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

zFENCE: Data-less Coherence for Efficient Fences.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

2014
Race detection for event-driven mobile applications.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2014

Using web corpus statistics for program analysis.
Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, 2014

Reducing MapReduce Abstraction Costs for Text-centric Applications.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

EFetch: optimizing instruction fetch for event-driven webapplications.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
A Safety-First Approach to Memory Models.
IEEE Micro, 2013

Catnap: energy proportional multiple network-on-chip.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

...And Region Serializability for All.
Proceedings of the 5th USENIX Workshop on Hot Topics in Parallelism, 2013

Parallelizing data race detection.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
DoublePlay: Parallelizing Sequential Logging and Replay.
ACM Trans. Comput. Syst., 2012

Chimera: hybrid program analysis for determinism.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012

Maple: a coverage-driven testing tool for multithreaded programs.
Proceedings of the 27th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2012

End-to-end sequential consistency.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

When less is more (LIMO): controlled parallelism forimproved efficiency.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Detecting and surviving data races using complementary schedules.
Proceedings of the 23rd ACM Symposium on Operating Systems Principles 2011, 2011

A case for an SC-preserving compiler.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Offline symbolic analysis to infer Total Store Order.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

MLP aware heterogeneous memory system.
Proceedings of the Design, Automation and Test in Europe, 2011

Efficient processor support for DRFx, a memory model with exceptions.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2010
DRFX: a simple and efficient memory model for concurrent programming languages.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Tolerating Concurrency Bugs Using Transactions as Lifeguards.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Respec: efficient online multiprocessor replayvia speculation and external determinism.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
LiteRace: effective sampling for lightweight data-race detection.
Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009

Offline symbolic analysis for multi-processor execution replay.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

A case for an interleaving constrained shared-memory multi-processor.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2007
Deterministic replay using processor support and its applications.
PhD thesis, 2007

Patching Processor Design Errors with Programmable Hardware.
IEEE Micro, 2007

Accelerating Meta Data Checks for Software Correctness and Security.
J. Instr. Level Parallelism, 2007

Automatically classifying benign and harmful data racesallusing replay analysis.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Bounds Checking with Taint-Based Analysis.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Transient fault prediction based on anomalies in processor events.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
BugNet: Recording Application-Level Execution for Deterministic Replay Debugging.
IEEE Micro, 2006

Software Profiling for Deterministic Replay Debugging of User Code.
Proceedings of the New Trends in Software Methodologies, Tools and Techniques, 2006

Automatic logging of operating system effects to guide application-level architecture simulation.
Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, 2006

Patching Processor Design Errors.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Recording shared memory dependencies using strata.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

Unbounded page-based transactional memory.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

A Dependency Chain Clustered Microarchitecture.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Creating Converged Trace Schedules Using String Matching.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003
Catching Accurate Profiles in Hardwar.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003


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