Sung-Gun Cho

Orcid: 0000-0001-6934-6956

According to our database1, Sung-Gun Cho authored at least 12 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits, April, 2024

2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.
IEEE J. Solid State Circuits, 2021

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2019
A 3.25Gb/s, 13.2pJ/b, 0.64mm<sup>2</sup> Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 2.56-mm<sup>2</sup> 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS.
IEEE J. Solid State Circuits, 2018

2017
Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

A 2.56mm<sup>2</sup> 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Error patterns in belief propagation decoding of polar codes and their mitigation methods.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2014
Block-Wise Concatenated BCH Codes for NAND Flash Memories.
IEEE Trans. Commun., 2014

2012
Concatenated BCH codes for NAND flash memories.
Proceedings of IEEE International Conference on Communications, 2012


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