Cheng-Hsun Lu

According to our database, Cheng-Hsun Lu authored at least 5 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing.

Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang

IEEE Trans. Computers, May, 2024

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.

Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

IEEE J. Solid State Circuits, April, 2024

An 11.4mm² 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications.

Cheng-Hsun Lu, Wei Tang, Jiyoon Han, Zhengya Zhang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm² AIB 2.0 Interface to Provide Versatile Workload Acceleration.

Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2019

A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training.

Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019