Yaoyu Tao
Orcid: 0000-0001-7500-5250
According to our database1,
Yaoyu Tao
authored at least 19 papers
between 2012 and 2024.
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Bibliography
2024
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration.
IEEE J. Solid State Circuits, April, 2024
2023
Hadamard product-based in-memory computing design for floating point neural network training.
Neuromorph. Comput. Eng., March, 2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture.
IEEE J. Solid State Circuits, 2021
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE Global Communications Conference, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 3.25Gb/s, 13.2pJ/b, 0.64mm<sup>2</sup> Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2015
IEEE J. Solid State Circuits, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
2013
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012