T. R. Viswanathan

According to our database, T. R. Viswanathan authored at least 27 papers between 1993 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC.

Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, T. R. Viswanathan

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

2021

A Novel Low-Power Single-step Subranging Open-loop Sigma-Delta ADC.

Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, Thayamkulangara R. Viswanathan

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020

Level-Crossing Detection based Low-Power Sigma-Delta ADC for Sensor Applications.

Sudhanva Vasishta, K. R. Raghunandan, Ananth Dodabalapur, T. R. Viswanathan

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2014

Analog signal processing in deep submicron CMOS technologies using inverters.

K. R. Raghunandan, Nan Sun, T. R. Viswanathan

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC.

Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping.

Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan, Nan Sun

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Linear current-controlled oscillator for analog to digital conversion.

K. R. Raghunandan, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Harmonic Rejection Mixing Techniques Using Clock-Gating.

Aslam A. Rafi, T. R. Viswanathan

IEEE J. Solid State Circuits, 2013

Operational current to frequency converter.

Rohit Yadav, K. R. Raghunandan, Ananth Dodabalapur, T. Lakshmi Viswanathan, T. R. Viswanathan

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A digital bandgap reference.

Adriana Becker-Gomez, Antonio F. Mondragón-Torres, Venkatesh Acharya, Bhaskar Banerjee, Thayamkulangara R. Viswanathan

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012

Clock-gated harmonic rejection mixers.

Aslam A. Rafi, T. R. Viswanathan

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC.

Joseph Hamilton, Shouli Yan, T. R. Viswanathan

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs.

Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan

IEEE Trans. Very Large Scale Integr. Syst., 2011

Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems.

Ajay Taparia, Bhaskar Banerjee, Thayamkulangara R. Viswanathan

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Two-Stage ADC Architecture With VCO-Based Second Stage.

Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010

A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator.

Joseph Hamilton, Shouli Yan, T. R. Viswanathan

IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009

Self-Biased Unity-Gain Buffers With Low Gain Error.

Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

A Low-Supply-Voltage CMOS Sub-Bandgap Reference.

Adriana Becker-Gomez, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems.

Ajay Taparia, Thayamkulangara R. Viswanathan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A highly linear CMOS current-controlled oscillator using a novel frequency detector.

Su Cui, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan, Bhaskar Banerjee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

CMOS Latch Using Quad for High-Speed Comparators.

Venkatesh Acharya, T. Lakshmi Viswanathan, Thayamkulangara R. Viswanathan

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 1.4 V Supply CMOS Fractional Bandgap Reference.

Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan

IEEE J. Solid State Circuits, 2007

2006

A Unity-Gain Buffer with Reduced Offset and Gain Error.

Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2002

A CMOS bandgap reference without resistors.

Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan

IEEE J. Solid State Circuits, 2002

2000

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process.

Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan

IEEE J. Solid State Circuits, 2000

1999

Efficient 6-bit A/D converter using a 1-bit folding front end.

K. Nagaraj, F. Chen, T. R. Viswanathan

IEEE J. Solid State Circuits, 1999

1993

A Non-uniform Sampling Technique for A/D Conversion.

N. Sayiner, Henrik V. Sorensen, T. R. Viswanathan

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993