Tao Yang

Orcid: 0000-0001-8588-9483

Affiliations:
  • Huawei Technologies Company Ltd., Shenzhen, China
  • Shanghai Jiao Tong University, China (PhD 2023)


According to our database1, Tao Yang authored at least 29 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2025
LCD: Advancing Extreme Low-Bit Clustering for Large Language Models via Knowledge Distillation.
CoRR, June, 2025

DASH: Input-Aware Dynamic Layer Skipping for Efficient LLM Inference with Markov Decision Policies.
CoRR, May, 2025

SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

2024
UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

T-BUS: Taming Bipartite Unstructured Sparsity for Energy-Efficient DNN Acceleration.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

Sava: A Spatial- and Value-Aware Accelerator for Point Cloud Transformer.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A Point Cloud Video Recognition Acceleration Framework Based on Tempo-Spatial Information.
IEEE Trans. Parallel Distributed Syst., December, 2023

DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

HyperAttack: An Efficient Attack Framework for HyperDimensional Computing.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN.
CoRR, 2022

Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization.
ACM Trans. Reconfigurable Technol. Syst., 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
CoRR, 2021

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs.
Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021

2020
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020


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