Thejas Kempanna

According to our database1, Thejas Kempanna authored at least 2 papers between 2016 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018

2016
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016


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