Ramesh Raghavan

According to our database, Ramesh Raghavan authored at least 4 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Validating Navmesh using Geometry: Voxel-Based Analysis with Prioritized Exploration.

Ramesh Raghavan, Ojas Sharma, Sebastien Larrue, Alan Isaac Kunder, Aakash Sai, Rishi Mathur

CoRR, May, 2026

2022

Optimized building extraction from high-resolution satellite imagery using deep learning.

Ramesh Raghavan, Dinesh Chander Verma, Digvijay Pandey, Rohit Anand, Binay Kumar Pandey, Harinder Singh

Multim. Tools Appl., 2022

2018

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.

Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2018

2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.

Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016