# Janakiraman Viraraghavan

According to our database

Collaborative distances:

^{1}, Janakiraman Viraraghavan authored at least 9 papers between 2008 and 2020.Collaborative distances:

## Timeline

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Book In proceedings Article PhD thesis Other## Links

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## Bibliography

2020

IET Circuits Devices Syst., 2020

2018

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.

IEEE J. Solid State Circuits, 2018

2016

IEEE J. Solid State Circuits, 2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2012

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.

J. Low Power Electron., 2008

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008