Janakiraman Viraraghavan

According to our database1, Janakiraman Viraraghavan authored at least 9 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Statistical compact model extraction for skew-normal distributions.
IET Circuits Devices Syst., 2020

2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018

2016
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits, 2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2012
Statistical Compact Model Extraction: A Neural Network Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2010
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.
J. Low Power Electron., 2008

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008


  Loading...