According to our database1, Balaji Jayaraman authored at least 10 papers between 2007 and 2020.
Legend:Book In proceedings Article PhD thesis Other
Assessment of end-to-end and sequential data-driven learning for non-intrusive modeling of fluid flows.
Adv. Comput. Math., 2020
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018
Proceedings of the Advances in Robotics, 2017
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
J. Comput. Phys., 2010
Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology.
J. Low Power Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007