Derek Leu

According to our database, Derek Leu authored at least 3 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.

Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2018

2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.

Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.

Chandrasekharan Kothandaraman, X. Chen, Dan Moy, D. Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, J. B. Johnson, Norman Robson, Subramanian S. Iyer

Proceedings of the IEEE International Reliability Physics Symposium, 2015