Thomas Popp

Orcid: 0000-0002-1970-8733

According to our database1, Thomas Popp authored at least 17 papers between 2005 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Systematic Propagation of AVHRR AOD Uncertainties - A Case Study to Demonstrate the FIDUCEO Approach.
Remote. Sens., 2022

2021
Potential and Challenges of Harmonizing 40 Years of AVHRR Data: The TIMELINE Experience.
Remote. Sens., 2021

2018
Quantifying Uncertainty in Satellite-Retrieved Land Surface Temperature from Cloud Detection Errors.
Remote. Sens., 2018

2016
Development, Production and Evaluation of Aerosol Climate Data Records from European Satellite Observations (Aerosol_cci).
Remote. Sens., 2016

2010
Algebraic Side-Channel Analysis in the Presence of Errors.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2009
An introduction to implementation attacks and countermeasures.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Practical Attacks on Masked Hardware.
Proceedings of the Topics in Cryptology, 2009

Evaluation of a DPA-Resistant Prototype Chip.
Proceedings of the Twenty-Fifth Annual Computer Security Applications Conference, 2009

2008
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box.
J. Signal Process. Syst., 2008

2007
Power Analysis Attacks and Countermeasures.
IEEE Des. Test Comput., 2007

Evaluation of the Masked Logic Style MDPL on a Prototype Chip.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

Power analysis attacks - revealing the secrets of smart cards.
Springer, ISBN: 978-0-387-30857-9, 2007

2006
Implementation aspects of the DPA-resistant logic style MDPL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Side channel analysis resistant design flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Configurable logic style translation based on an openaccess engine.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Side-Channel Leakage of Masked CMOS Gates.
Proceedings of the Topics in Cryptology, 2005

Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005


  Loading...