Timothy G. Rogers

Orcid: 0009-0002-0736-3149

According to our database1, Timothy G. Rogers authored at least 29 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Mitigating GPU Core Partitioning Performance Effects.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
SIMR: Single Instruction Multiple Request Processing for Energy-Efficient Data Center Microservices.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

A SIMT Analyzer for Multi-Threaded CPU Applications.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021
AccelWattch: A Power Modeling Framework for Modern GPUs.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Characterizing Massively Parallel Polymorphism.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Deadline-Aware Offloading for High-Throughput Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Judging a type by its pointer: optimizing GPU virtual functions.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Locality-Centric Data and Threadblock Management for Massive GPUs.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Deterministic Atomic Buffering.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Dimensionality-Aware Redundant SIMT Instruction Elimination.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Pagoda: A GPU Runtime System for Narrow Tasks.
ACM Trans. Parallel Comput., 2019

Analyzing Machine Learning Workloads Using a Detailed GPU Simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

A Detailed Model for Contemporary GPU Memory Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

POSTER: Quantifying the Direct Overhead of Virtual Function Calls on Massively Parallel Architectures.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
General-Purpose Graphics Processor Architectures
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01759-9, 2018

A Quantitative Evaluation of Contemporary GPU Simulation Methodology.
Proc. ACM Meas. Anal. Comput. Syst., 2018

Exploring Modern GPU Memory System Design Challenges through Accurate Modeling.
CoRR, 2018

Characterizing the Runtime Effects of Object-Oriented Workloads on GPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Pagoda: Fine-Grained GPU Resource Virtualization for Narrow Tasks.
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017

2016
POSTER: Pagoda: A Runtime System to Maximize GPU Utilization in Data Parallel Tasks with Limited Parallelism.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
A variable warp size architecture.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Learning your limit: managing massively multithreaded caches through scheduling.
Commun. ACM, 2014

2013
Cache-Conscious Thread Scheduling for Massively Multithreaded Processors.
IEEE Micro, 2013

Divergence-aware warp scheduling.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Cache-Conscious Wavefront Scheduling.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012


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