Tom Burd

According to our database1, Tom Burd authored at least 7 papers between 2008 and 2023.

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Bibliography

2023

Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2017
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management.
IEEE J. Solid State Circuits, 2017

2016
Carrizo: A High Performance, Energy Efficient 28 nm APU.
IEEE J. Solid State Circuits, 2016

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2009
Constraint Management and Checking in Template-Based Circuit Designs.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2008
Context-sensitive static transistor-level IR analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008


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