Tong-Yu Hsieh
Orcid: 0000-0002-7954-5569
According to our database1,
Tong-Yu Hsieh
authored at least 48 papers
between 2005 and 2023.
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Bibliography
2023
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4.
Proceedings of the IEEE International Test Conference in Asia, 2023
2022
On No-Reference Error Detection of an Image Stitching System Based on Error-Tolerance.
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Investigation on Error-Tolerability Enhancement of Videos via Re-Encoding for Computer Vision: A Case Study on Object Detection.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2020
An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications.
ACM Trans. Design Autom. Electr. Syst., 2020
On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
On Enhancing Error-Tolerability of Videos via Re-Encoding with Adaptive I-Frame Insertion.
Proceedings of the IEEE International Test Conference in Asia, 2020
A Self-Detection and Self-Repair Methodology for Reliable Speech Recognition Considering AWGN Noises.
Proceedings of the IEEE International Test Conference in Asia, 2020
2019
A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection.
Proceedings of the IEEE International Test Conference in Asia, 2019
On Automatic Generation of Training Images for Machine Learning in Automotive Applications.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
On Probability of Detection Lossless Concurrent Error Detection Based on Implications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
A No-Reference Error-Tolerability Test Methodology for Image Processing Applications.
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications.
Microelectron. J., 2017
A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability.
Proceedings of the International Test Conference in Asia, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEICE Trans. Electron., 2016
2015
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement.
J. Electron. Test., 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
J. Electron. Test., 2014
Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation.
J. Electron. Test., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
On efficient error-tolerability evaluation and maximization for image processing applications.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Output-bit selection with X-avoidance using multiple counters for test-response compaction.
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 22nd Asian Test Symposium, 2013
An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Proceedings of the 2009 IEEE International Test Conference, 2009
2008
IEEE Trans. Reliab., 2008
2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005