Toru Koizumi

According to our database, Toru Koizumi authored at least 18 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores.

Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

IEEE Comput. Archit. Lett., 2026

2025

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA.

Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya

IEICE Trans. Inf. Syst., 2025

Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors.

Fan Yang, Toru Koizumi, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI Applications.

Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Toru Koizumi, Ryota Shioya, Kei Ishii

Proceedings of the IEEE Hot Chips 37 Symposium, 2025

Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units.

Toru Koizumi, Ryota Shioya, Takuya Yamauchi, Tomoya Adachi, Ken Namura, Jun Makino

Proceedings of the IEEE 32nd Symposium on Computer Arithmetic, 2025

2023

A Principal Factor of Performance in Decoupled Front-End.

Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

IEICE Trans. Inf. Syst., December, 2023

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.

Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.

Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.

Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.

Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

2022

T-SKID: Predicting When to Prefetch Separately from Address Prediction.

Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.

Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Compiling and Optimizing Real-world Programs for STRAIGHT ISA.

Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A High-Performance Out-of-Order Soft Processor Without Register Renaming.

Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.

Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

STRAIGHT: Hazardless Processor Architecture Without Register Renaming.

Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Reduction of Instruction Increase Overhead by STRAIGHT Compiler.

Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.

Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the International Conference on Field-Programmable Technology, 2018