Hidetsugu Irie

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

T-SKID: Predicting When to Prefetch Separately from Address Prediction.

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[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Toward Wirelessly Cooperated Shape-Changing Computing Particles.

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[DOI]

IEEE Pervasive Comput., 2021

Multiport Register File Design for High-Performance Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.

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[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Compiling and Optimizing Real-world Programs for STRAIGHT ISA.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A High-Performance Out-of-Order Soft Processor Without Register Renaming.

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[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces.

[BibT_eX]

[DOI]

Proceedings of the AsianCHI '20: Proceedings of the 2020 Symposium on Emerging Research from Asia and on Asian Contexts and Cultures, 2020

An Inductively Coupled Wireless Bus for Chiplet-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

STRAIGHT: Hazardless Processor Architecture Without Register Renaming.

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[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Estimating driver's readiness by understanding driving posture.

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[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Reduction of Instruction Increase Overhead by STRAIGHT Compiler.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

Accelerating Integrity Verification on Secure Processors by Promissory Hash.

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[DOI]

Mizuki Miyanaga

Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

2016

High-Accuracy Joint Position Estimation and Posture Detection System for Driving.

[BibT_eX]

[DOI]

Takahiro Yamada

Proceedings of the Adjunct Proceedings of the 13th International Conference on Mobile and Ubiquitous Systems: Computing Networking and Services, 2016

"Stubborn" strategy to mitigate remaining cache misses.

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[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Design and Evaluation of a Configurable Query Processing Hardware for Data Streams.

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[DOI]

IEICE Trans. Inf. Syst., 2015

2014

An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications.

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[DOI]

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage.

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[DOI]

Proceedings of the Second International Symposium on Computing and Networking, 2014

2013

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

Sharing Computing Resources with Virtual Machines by Transparent Data Access.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Computing and Networking, 2013

A real-time gait improvement tool using a smartphone.

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[DOI]

Proceedings of the 4th Augmented Human International Conference, 2013

2012

Using Cacheline Reuse Characteristics for Prefetcher Throttling.

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[DOI]

IEICE Trans. Inf. Syst., 2012

Throttling Control for Bufferless Routing in On-chip Networks.

[BibT_eX]

[DOI]

Yicheng Guan

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers.

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[DOI]

Proceedings of the Third International Conference on Networking and Computing, 2012

Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion.

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[DOI]

Proceedings of the Third International Conference on Networking and Computing, 2012

FLAT: a GPU programming framework to provide embedded MPI.

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[DOI]

Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, 2012

2011

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2011

Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Networking and Computing, 2011

CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Networking and Computing, 2011

2010

OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip.

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[DOI]

Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010

Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster.

[BibT_eX]

[DOI]

Proceedings of the First International Conference on Networking and Computing, 2010

CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution.

[BibT_eX]

[DOI]

Proceedings of the First International Conference on Networking and Computing, 2010

An Efficient Path Setup for a Photonic Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the First International Conference on Networking and Computing, 2010

2008

Ultra Dependable Processor.

[BibT_eX]

[DOI]

Masahiro Goshima