Toshio Sunaga

According to our database, Toshio Sunaga authored at least 9 papers between 1992 and 1997.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1997

An eight-bit prefetch circuit for high-bandwidth DRAM's.

Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi

IEEE J. Solid State Circuits, 1997

1996

A parallel processing chip with embedded DRAM macros.

Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter

IEEE J. Solid State Circuits, 1996

A full bit prefetch DRAM sensing circuit.

Toshio Sunaga

IEEE J. Solid State Circuits, 1996

1995

A variable precharge voltage sensing.

Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira

IEEE J. Solid State Circuits, January, 1995

A 64Kb - 32 DRAM for graphics applications.

Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura

IBM J. Res. Dev., 1995

Combined DRAM and logic chip for massively parallel systems.

Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994

A 30-ns cycle time 4-Mb mask ROM.

Toshio Sunaga

IEEE J. Solid State Circuits, November, 1994

1992

A 14-ns 14-Mb CMOS DRAM with 300-mW active power.

Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa

IEEE J. Solid State Circuits, September, 1992

A pulsed sensing scheme with a limited bit-line swing.

Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong

IEEE J. Solid State Circuits, April, 1992