Susumu Imaoka

According to our database, Susumu Imaoka authored at least 8 papers between 2004 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.

Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2009

2008

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2008

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2008

2007

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2007

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.

Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.

Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.

Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade

IEEE J. Solid State Circuits, 2004