Toshiyuki Tsutsumi

According to our database1, Toshiyuki Tsutsumi authored at least 19 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Microprocessor Instruction Design Tool for RISC-V Architecture.
Proceedings of the 22nd International Symposium on Communications and Information Technologies, 2023

2022
Initial Implementation and Utilization of Instruction Dynamic Simulation in MEIMAT.
Proceedings of the 21st International Symposium on Communications and Information Technologies, 2022

Visualization Tool of Microprocessor Instruction for Designing New Architecture with Meta-Instructions.
Proceedings of the 21st International Symposium on Communications and Information Technologies, 2022

2019
Early Development of Visualization Tool for Instruction Implement of Microprocessor.
Proceedings of the 19th International Symposium on Communications and Information Technologies, 2019

2015
Impacts of flexible <i>V<sub>th</sub></i> control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs.
IEICE Electron. Express, 2015

2013
Fully-functional FPGA prototype with fine-grain programmable body biasing.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.
Proceedings of the 22nd Asian Test Symposium, 2013

2009
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

New Class of Tests for Open Faults with Considering Adjacent Lines.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
ACM Trans. Reconfigurable Technol. Syst., 2008

2007
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA.
IEICE Trans. Inf. Syst., 2007

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Optimal set of body bias voltages for an FPGA with field-programmable V<sub>th</sub> components.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Evaluation of granularity on threshold voltage control in flex power FPGA.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2004
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity.
IEICE Trans. Inf. Syst., 2004

Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004


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