Yasuhiro Ogasahara

According to our database1, Yasuhiro Ogasahara authored at least 21 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr., 2020

Prototype of USB stick-sized PUF module for authentication and key generation.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

Implementation of pseudo linear feedback shift register physical unclonable function on silicon.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM.
IEEE Micro, 2015

Impacts of flexible <i>V<sub>th</sub></i> control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs.
IEICE Electron. Express, 2015

Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate.
IEICE Electron. Express, 2014

Supply Noise Suppression by Triple-Well Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2013

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform.
IEEE J. Solid State Circuits, 2009

Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects.
IEEE J. Solid State Circuits, 2008

Impact of Well Edge Proximity Effect on Timing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

W-CDMA Channel Codec by Configurable Processors.
Intell. Autom. Soft Comput., 2006

Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Measurement and analysis of delay variation due to inductive coupling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005