Takashi Aikyo

According to our database1, Takashi Aikyo authored at least 30 papers between 1986 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
A Variability-Aware Adaptive Test Flow for Test Quality Improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012
Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool.
IEICE Trans. Inf. Syst., 2012

2011
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.
IEICE Trans. Inf. Syst., 2011

2010
A Study of Capture-Safe Test Generation Flow for At-Speed Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Small Delay Fault Model for Intra-Gate Resistive Open Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Diagnostic test generation for transition faults using a stuck-at ATPG tool.
Proceedings of the 2009 IEEE International Test Conference, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Estimation of Delay Test Quality and Its Application to Test Generation.
IPSJ Trans. Syst. LSI Des. Methodol., 2008

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.
IEICE Trans. Inf. Syst., 2008

Post-BIST Fault Diagnosis for Multiple Faults.
IEICE Trans. Inf. Syst., 2008

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate.
IEICE Trans. Inf. Syst., 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.
Proceedings of the 13th European Test Symposium, 2008

2007
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Timing-Aware Diagnosis for Small Delay Defects.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Test Roles in Diagnosis and Silicon Debug.
Proceedings of the 16th Asian Test Symposium, 2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Test Data Compression of 100x for Scan-Based BIST.
Proceedings of the 2006 IEEE International Test Conference, 2006

Effective Post-BIST Fault Diagnosis for Multiple Faults.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.
Proceedings of the 15th Asian Test Symposium, 2006

At-Speed Testing with Timing Exceptions and Constraints-Case Studies.
Proceedings of the 15th Asian Test Symposium, 2006

2000
Issues on SOC testing in DSM area: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000

1997
A Test Synthesis Approach to Reducing BALLAST DFT Overhead.
Proceedings of the 34st Conference on Design Automation, 1997

ATREX : Design for Testability System for Mega Gate LSIs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1990
ASIC CAD system based on hierarchical design-for-testability.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1986
An Automatic Test Generation System for Large Scale Gate Arrays.
Proceedings of the Spring COMPCON'86, 1986


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