Tuo Li

Orcid: 0000-0003-2664-822X

Affiliations:
  • University of New South Wales, Australia


According to our database1, Tuo Li authored at least 20 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks.
CoRR, 2022

HWST128: complete memory safety accelerator on RISC-V with metadata compression.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

FaSe: fast selective flushing to mitigate contention-based cache timing attacks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
COPS: A complete oblivious processing system.
Microprocess. Microsystems, September, 2021

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Hardware Trojan Mitigation in Pipelined MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2020

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation.
CoRR, 2020

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

2017
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
IEEE Trans. Computers, 2017

2016
Processor Design for Soft Errors: Challenges and State of the Art.
ACM Comput. Surv., 2016

RECORD: Reducing register traffic for checkpointing in embedded processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA.
Proceedings of the 28th International Conference on VLSI Design, 2015

Side channel attacks in embedded systems: A tale of hostilities and deterrence.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.
PhD thesis, 2013

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Fine-grained hardware/software methodology for process migration in MPSoCs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012


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