Valerio Pica

According to our database, Valerio Pica authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Asymmetric and Adaptive Error Correction in STT-MRAM.

Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Valerio Pica, Gouri Sankar Kar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025

2024

Soft and Hard Error-Correction Techniques in STT-MRAM.

Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Valerio Pica, Gouri Sankar Kar

IEEE Des. Test, October, 2024

Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer.

Farrukh Yasin, A. Palomino, A. Kumar, Valerio Pica, Simon Van Beek, Giacomo Talmelli, Van D. Nguyen, Stefan Cosemans, D. Crotti, Kurt Wostyn, Gouri Sankar Kar, Sebastien Couet

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays.

W. Kim, Valerio Pica, N. Jossart, Farrukh Yasin, Kurt Wostyn, S. Couet, Sidharth Rao

Proceedings of the IEEE International Memory Workshop, 2024