Gouri Sankar Kar
According to our database1,
Gouri Sankar Kar
authored at least 54 papers
between 2006 and 2023.
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Bibliography
2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Lowest IOFF < 3×10<sup>-21</sup> A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs.
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays.
Proceedings of the IEEE International Memory Workshop, 2023
Understanding the impact of La dopant position on the ferroelectric properties of hafnium zirconate.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
NPN Si/SiGe memory selector with non-linearity>10<sup>5</sup> and ON-current>6MA/cm<sup>2</sup>.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control.
Proceedings of the International Conference on IC Design and Technology, 2022
Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Threshold switching in a-Si and a-Ge based MSM selectors and its implications for device reliability.
Proceedings of the IEEE International Memory Workshop, 2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021
Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs.
Proceedings of the IEEE International Test Conference, 2020
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Enhancement of CBRAM performance by controlled formation of a hourglass-shaped filament.
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2015
Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2006
Microelectron. J., 2006