Farrukh Yasin

According to our database, Farrukh Yasin authored at least 8 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications.

Siddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet

Proceedings of the IEEE International Memory Workshop, 2023

2021

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.

Simon Van Beek, Siddharth Rao, Shreya Kundu, Woojin Kim, Barry J. O'Sullivan, Stefan Cosemans, Farrukh Yasin, Robert Carpenter, Sebastien Couet, Shamin H. Sharifi, Nico Jossart, Davide Crotti, Gouri Sankar Kar

Proceedings of the IEEE International Reliability Physics Symposium, 2021

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.

Sidharth Rao, Woojin Kim, Simon Van Beek, Shreya Kundu, Manu Perumkunnil, Stefan Cosemans, Farrukh Yasin, Sebastien Couet, Robert Carpenter, Barry J. O'Sullivan, Shamin H. Sharifi, N. Jossart, Laurent Souriau, Ludovic Goux, Dimitri Crotti, Gouri Sankar Kar

Proceedings of the IEEE International Memory Workshop, 2021

2019

Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM.

Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet, Laurent Souriau, Shamin H. Sharifi, Johan Swerts, Robert Carpenter, Sidharth Rao, Wonsub Kim, J. Wu, K. K. V. Sethu, M. Pak, N. Jossart, D. Crotti, Arnaud Furnémont, Gouri Sankar Kar

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.

Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar

Proceedings of the 24th IEEE European Test Symposium, 2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.

Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

SOT-MRAM 300mm integration for low power and ultrafast embedded memories.

Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar

CoRR, 2018

Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.

Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao, Wonsub Kim, S. Couet, Johan Swerts, Farrukh Yasin, Dimitri Crotti, Dimitri Linten, Gouri Sankar Kar

Proceedings of the IEEE International Reliability Physics Symposium, 2018