Nico Jossart

According to our database1, Nico Jossart authored at least 7 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
MTJ degradation in multi-pillar SOT-MRAM with selective writing.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
MTJ degradation in SOT-MRAM by self-heating-induced diffusion.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
SOT-MRAM 300mm integration for low power and ultrafast embedded memories.
CoRR, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


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