Danil Sokolov

IEEE Trans. Very Large Scale Integr. Syst., 2020

Automating the Design of Asynchronous Logic Control for AMS Electronics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Empirical Temperature Model of Self-Directed Channel Memristor.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

Handshake Verification in WORKCRAFT.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019

Toward Designing Thermally-Aware Memristance Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Self-timed, minimum latency circuits for the internet of things.

[BibT_eX]

[DOI]

Integr., 2019

Synthesis from Waveform Transition Graphs.

[BibT_eX]

[DOI]

Alberto Moreno

Jordi Cortadella

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

Generalised Asynchronous Arbiter.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Application of Concurrency to System Design, 2019

2018

High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

An Excitation Time Model for General-purpose Memristance Tuning Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Reconfigurable asynchronous pipelines: From formal models to silicon.

[BibT_eX]

[DOI]

Alessandro de Gennaro

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

Loadable Kessels Counter.

[BibT_eX]

[DOI]

Oyinkuro Benafa

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017

A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits.

[BibT_eX]

[DOI]

Frank P. Burns

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Power proportional adder design for Internet of Things in a 65 nm process.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Pulse controlled memristor-based delay element.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Asynchronous Arbitration Primitives for New Generation of Circuits and Systems.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Self-timed control of multiphase switched capacitor converters.

[BibT_eX]

[DOI]

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Benefits of asynchronous control for analog electronics: Multiphase buck case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy-efficient approximate multiplier design using bit significance-driven logic compression.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

WAITX: An Arbiter for Non-persistent Signals.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity.

[BibT_eX]

[DOI]

Johnson Fernandes

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Formal Design and Verification of an Asynchronous SRAM Controller.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

2016

Design of Mixed-Signal Systems With Asynchronous Control.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis.

[BibT_eX]

[DOI]

Mahdi Jelodari Mamaghani

Jim D. Garside

Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016

2015

Persistent and Nonviolent Steps and the Design of GALS Systems.

[BibT_eX]

[DOI]

Johnson Fernandes

Maciej Koutny

Lukasz Mikulski

Marta Pietkiewicz-Koutny

Fundam. Informaticae, 2015

Compositional design of asynchronous circuits from behavioural concepts.

[BibT_eX]

[DOI]

Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Wireless data and power transfer of an optogenetic implantable visual cortex stimulator.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

GALS synthesis and verification for xMAS models.

[BibT_eX]

[DOI]

Frank P. Burns

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A CMOS-based neural implantable optrode for optogenetic stimulation and electrical recording.

[BibT_eX]

[DOI]

Timothy G. Constandinou

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Design and Verification of Speed-Independent Multiphase Buck Controller.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Opportunistic Merge Element.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014

Synthesis of Processor Instruction Sets from High-Level ISA Specifications.

[BibT_eX]

[DOI]

Alexander B. Romanovsky

IEEE Trans. Computers, 2014

Design of safety critical systems by refinement.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An implantable optrode with Self-diagnostic function in 0.35µm CMOS for optical neural stimulation.

[BibT_eX]

[DOI]

Hubin Zhao

Patrick Degenaar

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013

Design-for-adaptivity of microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Step Persistence in the Design of GALS Systems.

[BibT_eX]

[DOI]

Johnson Fernandes

Maciej Koutny

Marta Pietkiewicz-Koutny

Proceedings of the Application and Theory of Petri Nets and Concurrency, 2013

2012

Towards power-elastic systems through concurrency management.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

On Dual-Rail Control Logic for Enhanced Circuit Robustness.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011

Formal modelling and transformations of processor instruction sets.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

2008

Analysis of Static Data Flow Structures.

[BibT_eX]

[DOI]

Ivan Poliakov

Fundam. Informaticae, 2008

Conversion driven design of binary to mixed radix circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Automated Verification of Asynchronous Circuits Using Circuit Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007

Registers for Phase Difference Based Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Direct Mapping of Low-Latency Asynchronous Controllers From STGs.

[BibT_eX]

[DOI]

Alexandre V. Bystrov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Workcraft: A Static Data Flow Structure Editing, Visualisation and Analysis Tool.

[BibT_eX]

[DOI]

Ivan Poliakov

Proceedings of the Petri Nets and Other Models of Concurrency, 2007

Asynchronous Data Path Models.

[BibT_eX]

[DOI]

Ivan Poliakov

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006

Online Testing by Protocol Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Cost-aware synthesis of asynchronous circuits based on partial acknowledgement.

[BibT_eX]

[DOI]

Yu Zhou

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Design and Analysis of Dual-Rail Circuits for Security Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

2004

A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Improving the Security of Dual-Rail Circuits.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

2003

STG Optimisation in the Direct Mapping of Asynchronous Circuits .

[BibT_eX]

[DOI]

Alexandre V. Bystrov

Proceedings of the 2003 Design, 2003

Low-Latency Contro Structures with Slack.

[BibT_eX]

[DOI]

Alexandre V. Bystrov