Greg Yeric

Affiliations:

ARM Inc., Austin, TX, USA

According to our database¹, Greg Yeric authored at least 32 papers between 1990 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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On csauthors.net:

Bibliography

2022

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology.

[BibT_eX]

[DOI]

Saurabh V. Suryavanshi

Proceedings of the IEEE International Memory Workshop, 2022

2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.

[BibT_eX]

[DOI]

CoRR, 2021

2020

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.

[BibT_eX]

[DOI]

CoRR, 2020

2019

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

IC Design After Moore's Law.

[BibT_eX]

[DOI]

Greg Yeric

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK.

[BibT_eX]

[DOI]

CoRR, 2018

2017

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

ASAP7: A 7-nm finFET predictive process design kit.

[BibT_eX]

[DOI]

Chandarasekaran Ramamurthy

Greg Yeric

Microelectron. J., 2016

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

At the core of system scaling.

[BibT_eX]

[DOI]

Greg Yeric

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Match-making for monolithic 3D IC: finding the right technology node.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Circuit design perspectives for Ge FinFET at 10nm and beyond.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Power benefit study of monolithic 3D IC at the 7nm technology node.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Design, technology and yield in the post-moore era.

[BibT_eX]

[DOI]

Greg Yeric

Proceedings of the 2014 International Test Conference, 2014

Physical design and FinFETs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

2013

The past present and future of design-technology co-optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Design benchmarking to 7nm with FinFET predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Exploring sub-20nm FinFET design with predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Correlating models and silicon for improved parametric yield.

[BibT_eX]

[DOI]

Rob Aitken

Greg Yeric

David Flynn

Proceedings of the Design, Automation and Test in Europe, 2011

2007

Making Manufacturing Work For You.

[BibT_eX]

Srikanth Venkataraman

Proceedings of the 44th Design Automation Conference, 2007

2005

Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

1993

Improved universal MOSFET electron mobility degradation models for circuit simulation.

[BibT_eX]

[DOI]

C. Patrick Yue

Victor Martin Agostinelli Jr.

Gregory Munson Yeric

A. F. Tasch Jr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Universal MOSFET hole mobility degradation models for circuit simulation.

[BibT_eX]

[DOI]

Victor Martin Agostinelli Jr.

Gregory Munson Yeric

A. F. Tasch Jr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1990

A universal MOSFET mobility degradation model for circuit simulation.

[BibT_eX]

[DOI]

Gregory Munson Yeric

A. F. Tasch Jr.

Sanjay K. Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Greg Yeric

Timeline

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