Vineeth Govind

According to our database, Vineeth Govind authored at least 6 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers.

Pietro Saltarelli, Behrad Niazmand, Jaan Raik, Vineeth Govind, Thomas Hollstein, Gert Jervan, Ranganathan Hariharan

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2012

Ultra-low latency NoC testing via pseudo-random test pattern compaction.

Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi

Proceedings of the 2012 International Symposium on System on Chip, 2012

Low-area boundary BIST architecture for mesh-like network-on-chip.

Jaan Raik, Vineeth Govind

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2009

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips.

Jaan Raik, Vineeth Govind, Raimund Ubar

IET Comput. Digit. Tech., 2009

2007

Test Configurations for Diagnosing Faulty Links in NoC Switches.

Jaan Raik, Raimund Ubar, Vineeth Govind

Proceedings of the 12th European Test Symposium, 2007

2006

An External Test Approach for Network-on-a-Chip Switches.

Jaan Raik, Vineeth Govind, Raimund Ubar

Proceedings of the 15th Asian Test Symposium, 2006