Behrad Niazmand

Orcid: 0000-0002-3332-199X

According to our database1, Behrad Niazmand authored at least 23 papers between 2012 and 2020.

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Bibliography

2020
LiD-CAT: A Lightweight Detector for Cache ATtacks.
Proceedings of the IEEE European Test Symposium, 2020

2019
Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers.
Proceedings of the IEEE International Test Conference in Asia, 2018

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics.
Proceedings of the IEEE International Test Conference in Asia, 2018

Enabling Secure MPSoC Dynamic Operation through Protected Communication.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

From RTL Liveness Assertions to Cost-Effective Hardware Checkers.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Fault-resilient NoC router with transparent resource allocation.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Automated area and coverage optimization of minimal latency checkers.
Proceedings of the 22nd IEEE European Test Symposium, 2017

From online fault detection to fault management in Network-on-Chips: A ground-up approach.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems.
CoRR, 2016

SoCDep<sup>2</sup>: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Logic-based implementation of fault-tolerant routing in 3D network-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

2015
Automated minimization of concurrent online checkers for Network-on-Chips.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Mixed-criticality NoC partitioning based on the NoCDepend dependability technique.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
A loss aware scalable topology for photonic on chip interconnection networks.
J. Supercomput., 2014

2012
PathAware: A contention-aware selection function for application-specific Network-On-Chips.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012


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