Vinod Viswanath

According to our database, Vinod Viswanath authored at least 16 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications.

Vinod Viswanath, Kanad Chakraborty

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2019

Closing the Verification Gap with Static Sign-off.

Pranav Ashar, Vinod Viswanath

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2017

Failures and verification solutions related to untimed paths in SOCs.

Pranav Ashar, Vikas Sachdeva, Vinod Viswanath

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Welcome.

Brian Cline, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, Ali Iranmanesh

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2013

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs.

Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Jacob A. Abraham

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Power Management Methods: From Specification and Modeling, to Techniques and Verification.

Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Ananth S. Narayan

J. Low Power Electron., 2012

Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design.

Vinod Viswanath, Jacob A. Abraham

J. Low Power Electron., 2012

2009

Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level.

Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham

J. Low Power Electron., 2009

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL.

Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

Sequential equivalence checking between system level and RTL descriptions.

Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu

Des. Autom. Embed. Syst., 2008

2007

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.

Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham

IEEE Trans. Computers, 2007

Efficient Microprocessor Verification using Antecedent Conditioned Slicing.

Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.

Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Automatic insertion of low power annotations in RTL for pipelined microprocessors.

Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004

Multi-log Processor - Towards Scalable Event-Driven Multiprocessors.

Vinod Viswanath

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

1999

The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture.

Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999