Kanad Chakraborty

According to our database1, Kanad Chakraborty authored at least 24 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2013
Novel Self-Timed, Pipelined Clock Scan Architecture.
J. Electron. Test., 2013

2012
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®.
J. Electron. Test., 2012

2010
A MATLAB-based technique for defect level estimation using data mining of test fallout data versus fault coverage.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2008
A Randomized Greedy Method for Rectangular-Pattern Fill Problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2006
Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient Techniques for Noise Characterization of Sequential Cells and Macros.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.
J. Electron. Test., 2004

2002
A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation.
Inf. Process. Lett., 2002

A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
A physical design tool for built-in self-repairable RAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
New March Tests for Multiport RAM Devices.
J. Electron. Test., 2000

Transformational Placement and Synthesis.
Proceedings of the 2000 Design, 2000

1999
Congestion Mitigation During Placement.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Physical Design Tool for Built-in Self-Repairable Static RAMs.
Proceedings of the 1999 Design, 1999

1998
FTROM: A Silicon Compiler for Fault-tolerant ROMs.
Integr., 1998

A Silicon Compiler for Fault-Tolerant ROMs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
BISRAMGEN: A silicon compiler for built-in self-repairable random-access memories.
PhD thesis, 1997

A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs.
Proceedings of the European Design and Test Conference, 1997

1996
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994
Response to letter by Q. Hu and D. B. Hertz.
Neural Networks, 1994

Technology and layout-related testing of static random-access memories.
J. Electron. Test., 1994

1992
Forecasting the behavior of multivariate time series using neural networks.
Neural Networks, 1992


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