Christophe Layer

Orcid: 0000-0002-5229-072X

According to our database1, Christophe Layer authored at least 21 papers between 2003 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2017
Using quadrature modulation for precise fault location over wired communication channels.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Automated phase offset correction using reflectometry in fault detection systems.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A joint reflectometry-optimization algorithm for mapping the topology of an unknown wire network.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

On the phase analysis of multi-carrier signals for high-precision fault detection by reflectometry.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

Microsecond intermittent fault detection for wire and connector defect prognostics.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

Compressed signal acquisition in wire diagnostic.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Magnetic memories: From DRAM replacement to ultra low power logic chips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2011
The POWER7 Binary Floating-Point Unit.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2007
A coprocessor for fast searching in large databases: associative computing engine.
PhD thesis, 2007

Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Vertical Sorting Techniques Accelerating Associative Accesses based Information Retrieval Systems.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005

An Interactive Systemc Course Featuring Real-Time Online Compiling and Analysis.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
A scalable compact architecture for the computation of integer binary logarithms through linear approximation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data.
Proceedings of the Field Programmable Logic and Application, 2004

High Performance Associative Coprocessor Architecture for Advanced Database Searching.
Proceedings of the IASTED International Conference on Databases and Applications, 2004

2003
High Performance System Architecture of an Associative Computing Engine Optimised for Search Algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003


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