Weidong Kuang

According to our database1, Weidong Kuang authored at least 12 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Learning to Detect Pedestrian Flow in Traffic Intersections from Synthetic Data.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

2016
Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2013
Correction and Comment on "An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications".
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2011
Design of Sequential Elements for Low Power Clocking System.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
PMOS breakdown effects on digital circuits - Modeling and analysis.
Microelectron. Reliab., 2008

2007
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Low Power Domino with Differential-Controlled-Keeper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Hardening for Asynchronous Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2004
Teaching asynchronous design in digital integrated circuits.
IEEE Trans. Educ., 2004


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