Peiyi Zhao

According to our database1, Peiyi Zhao authored at least 17 papers between 2000 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
A clocked differential switch logic using floating-gate MOS transistors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011
Design of Sequential Elements for Low Power Clocking System.
IEEE Trans. VLSI Syst., 2011

2010
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design.
Signal Processing Systems, 2010

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. VLSI Syst., 2010

2009
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.
IEEE Trans. VLSI Syst., 2009

Incorporating real world integrated circuit in a liberal arts computer science program.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2008
Power analysis of the Huffman decoding tree.
Proceedings of the International Conference on Image Processing, 2008

2007
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.
IEEE Trans. VLSI Syst., 2007

PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A Low Power Domino with Differential-Controlled-Keeper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Hardening for Asynchronous Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
A low-power clock frequency multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
High-performance and low-power conditional discharge flip-flop.
IEEE Trans. VLSI Syst., 2004

A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Contention reduced/conditional discharge flip-flops for level conversion in CVS systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Low Power Conditional-Discharge Pulsed Flip-Flops.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

2000
On the isomorphism of expressions.
Inf. Process. Lett., 2000


  Loading...