Yu Bai

Orcid: 0000-0002-2303-1120

Affiliations:
  • California State University, School of Engineering and Computer Science, Fullerton, CA, USA
  • University of Central Florida, Orlando, FL, USA (PhD 2016)


According to our database1, Yu Bai authored at least 41 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Algorithm and hardware co-design co-optimization framework for LSTM accelerator using quantized fully decomposed tensor train.
Internet Things, July, 2023

Locality-sensing Fast Neural Network (LFNN): An Efficient Neural Network Acceleration Framework via Locality Sensing for Real-time Videos Queries.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural Network.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

2021
Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture.
IEEE Trans. Emerg. Top. Comput., 2021

An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Supervised Sentiment Analysis of Twitter Handle of President Trump with Data Visualization Technique.
Proceedings of the 10th Annual Computing and Communication Workshop and Conference, 2020

2019
Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers.
IEEE Trans. Emerg. Top. Comput., 2019

High Efficient Deep Feature Extraction and Classification of Spectral-Spatial Hyperspectral Image Using Cross Domain Convolutional Neural Networks.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019

Hyperspectral image classification with SVM and guided filter.
EURASIP J. Wirel. Commun. Netw., 2019

Information, knowledge, and semantics for interacting with Internet-of-Things.
Comput. Networks, 2019

Energy Efficient Mobile Service Computing With Differential Spintronic-C-Elements: A Logic-in-Memory Asynchronous Computing Paradigm.
IEEE Access, 2019

Compressing Deep Neural Networks Using Toeplitz Matrix: Algorithm Design and Fpga Implementation.
Proceedings of the IEEE International Conference on Acoustics, 2019

Multimodal Biometrics for Enhanced IoT Security.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Security, Privacy, and Usability Challenges in Selfie Biometrics.
Proceedings of the Selfie Biometrics - Advances and Challenges, 2019

2018
Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm.
IEEE Trans. Computers, 2018

An Adaptive SVR for High-Frequency Stock Price Forecasting.
IEEE Access, 2018

Spectral-Spatial HyperspectralImage Classification With K-Nearest Neighbor and Guided Filter.
IEEE Access, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Performance evaluation of ternary computation in SRAM design using graphene nanoribbon field effect transistors.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

FRLDM: Empowering K-nearest Neighbor (KNN) through FPGA-based Reduced-rank Local Distance Metric.
Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

2017
CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-CirculantWeight Matrices.
CoRR, 2017

High efficient reconfigurable PUF through spin hall-induced coupled-oscillators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

K-Nearest Neighbor combined with guided filter for hyperspectral image classification.
Proceedings of the 2017 International Conference on Identification, 2017

A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Artificial Haze Immune Algorithm for Image Processing.
Proceedings of the International Conference on Identification, 2016

Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Universal Random Number Generation with Field-Programmable Analog Array and Magnetic Tunneling Junction (MTJ) Devices.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Stochastically computing discrete Fourier transform with reconfigurable digital fabric.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience.
J. Electr. Comput. Eng., 2012

2011
Discriminatively Fortified Computing with Reconfigurable Digital Fabric.
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011


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