Qilin Zheng

According to our database, Qilin Zheng authored at least 20 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM.

Jonathan Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, J. V. Rajendran, Yiran Chen

CoRR, 2024

2023

EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference.

Yitu Wang, Shiyu Li, Qilin Zheng, Andrew Chang, Hai Li, Yiran Chen

ACM Trans. Embed. Comput. Syst., October, 2023

SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons.

Ziru Li, Qilin Zheng, Yiran Chen, Hai Helen Li

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.

Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst

IEEE J. Solid State Circuits, 2023

In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search.

Yitu Wang, Shiyu Li, Qilin Zheng, Linghao Song, Zongwang Li, Andrew Chang, Hai (Helen) Li, Yiran Chen

CoRR, 2023

SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models.

Zhixu Du, Shiyu Li, Yuhao Wu, Xiangyu Jiang, Jingwei Sun, Qilin Zheng, Yongkai Wu, Ang Li, Hai (Helen) Li, Yiran Chen

CoRR, 2023

Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators.

Xueying Wu, Edward Hanson, Nansu Wang, Qilin Zheng, Xiaoxuan Yang, Huanrui Yang, Shiyu Li, Feng Cheng, Partha Pratim Pande, Janardhan Rao Doppa, Krishnendu Chakrabarty, Hai Li

CoRR, 2023

Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture.

Qilin Zheng, Shiyu Li, Yitu Wang, Ziru Li, Yiran Chen, Hai Helen Li

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design.

Xiaoxuan Yang, Shiyu Li, Qilin Zheng, Yiran Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Device-Architecture Co-optimization for RRAM-based In-memory Computing.

Yimao Cai, Yi Gao, Zongwei Wang, Lin Bao, Ling Liang, Qilin Zheng, Cuimei Wang, Ru Huang

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Processing-in-Memory Technology for Machine Learning: From Basic to ASIC.

Brady Taylor, Qilin Zheng, Ziru Li, Shiyu Li, Yiran Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.

Qilin Zheng, Xingchen Li, Yijin Guan, Zongwei Wang, Yimao Cai, Yiran Chen, Guangyu Sun, Ru Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Large-scale full-programmable quantum walk and its applications.

Yizhi Wang, Yingwen Liu, Junwei Zhan, Shichuan Xue, Yuzhen Zheng, Ru Zeng, Zhihao Wu, Zihao Wang, Qilin Zheng, Dongyang Wang, Weixu Shi, Xiang Fu, Ping Xu, Yang Wang, Yong Liu, Jiangfang Ding, Guangyao Huang, Chunlin Yu, Anqi Huang, Xiaogang Qiang, Mingtang Deng, Weixia Xu, Kai Lu, Xuejun Yang, Junjie Wu

CoRR, 2022

Quantum algorithm and experimental demonstration for the subset sum problem.

Qilin Zheng, Pingyu Zhu, Shichuan Xue, Yang Wang, Chao Wu, Xinyao Yu, Miaomiao Yu, Yingwen Liu, Mingtang Deng, Junjie Wu, Ping Xu

Sci. China Inf. Sci., 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.

Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.

Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.

Qilin Zheng, Xingchen Li, Zongwei Wang, Guangyu Sun, Yimao Cai, Ru Huang, Yiran Chen, Hai Li

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.

Qilin Zheng, Jian Kang, Zongwei Wang, Yimao Cai, Ru Huang, Bing Li, Yiran Chen, Hai Helen Li

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Qilin Zheng, Zongwei Wang, Jian Kang, Zhizhen Yu, Yimao Cai, Jintong Xu

Proceedings of the Non-Volatile Memory Technology Symposium, 2018