Lei Shan

According to our database, Lei Shan authored at least 11 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2020

Impulse Feature Extraction of Bearing Faults Based on Convolutive Nonnegative Matrix Factorization.

Lin Liang, Lei Shan, Fei Liu, Maolin Li, Ben Niu, Guanghua Xu

IEEE Access, 2020

2017

Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks.

Naiyang Guan, Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang

Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Heterogeneous acceleration for CNN training with many integrated core.

Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang

Proceedings of the 2017 IEEE International Conference on Signal Processing, 2017

2016

A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network.

Lei Shan, Minxuan Zhang, Lin Deng, Guohui Gong

Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.

Lei Shan, He Wang, Weixia Xu, Canqun Yang, Minxuan Zhang

Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2015

2014

GI/Geom/1 queue based on communication model for mesh networks.

Wei Wei, Quan Xu, L. Wang, X. H. Hei, P. Shen, W. Shi, Lei Shan

Int. J. Commun. Syst., 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2006

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology.

John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman

IEEE J. Solid State Circuits, 2006

2003

SiGe BiCMOS integrated circuits for high-speed serial communication links.

Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer

IBM J. Res. Dev., 2003

2002

50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems.

Mounir Meghelli, Alexander V. Rylyakov, Lei Shan

IEEE J. Solid State Circuits, 2002