Wenjing Yin

Orcid: 0000-0003-1932-5561

According to our database1, Wenjing Yin authored at least 23 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Zero-Knowledge Proof Intelligent Recommendation System to Protect Students' Data Privacy in the Digital Age.
Appl. Artif. Intell., December, 2023

2022
Anomaly Detection in EM Images - A Zero-Shot Learning Approach.
Proceedings of the 19th IEEE International Symposium on Biomedical Imaging, 2022

Research on the Interactive Relationship of Immersive Art.
Proceedings of the Design, User Experience, and Usability: Design Thinking and Practice in Contemporary and Emerging Technologies, 2022

2021
Novel Pythagorean fuzzy entropy and Pythagorean fuzzy cross-entropy measures and their applications.
J. Intell. Fuzzy Syst., 2021

Research on Interactive Design of Public Art Landscape at Night.
Proceedings of the Design, User Experience, and Usability: Design for Contemporary Technological Environments, 2021

2020
Automatic Repair of Semantic Defects Using Restraint Mechanisms.
Symmetry, 2020

Priority Measurement of Patches for Program Repair Based on Semantic Distance.
Symmetry, 2020

Automated Program-Semantic Defect Repair and False-Positive Elimination without Side Effects.
Symmetry, 2020

Automated Neuron Shape Analysis from Electron Microscopy.
CoRR, 2020

Application of Interactive Design in Shanghai Public Art Practice.
Proceedings of the Design, User Experience, and Usability. Case Studies in Public and Personal Interactive Systems, 2020

Pedagogical Discussion on the Application of Role Immersion in Interior Design Teaching.
Proceedings of the Design, User Experience, and Usability. Case Studies in Public and Personal Interactive Systems, 2020

Automatic Repair of Semantic Defects Using Restraint Mechanisms.
Proceedings of the Frontiers in Cyber Security - Third International Conference, 2020

2019
Memory Leak Detection in IoT Program Based on an Abstract Memory Model SeqMM.
IEEE Access, 2019

2011
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
IEEE J. Solid State Circuits, 2011

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits, 2011

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.
IEEE J. Solid State Circuits, 2011

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2011

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007
A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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