Naga Sasidhar

According to our database1, Naga Sasidhar authored at least 5 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.
IEEE J. Solid State Circuits, 2011

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.
IEEE J. Solid State Circuits, 2009

2006
A Distortion Compensating Flash Analog-to-Digital Conversion Technique.
IEEE J. Solid State Circuits, 2006


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