Mrunmay Talegaonkar
Orcid: 0000-0003-2559-6915
According to our database1,
Mrunmay Talegaonkar
authored at least 30 papers
between 2011 and 2018.
Collaborative distances:
Collaborative distances:
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Bibliography
2018
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits, 2014
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4<sup>th</sup>-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011