Amr Elshazly

According to our database1, Amr Elshazly authored at least 45 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET.
J. Solid-State Circuits, 2019

2018
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.
IEEE Trans. on Circuits and Systems, 2018

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.
J. Solid-State Circuits, 2018

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.
IEEE Trans. on Circuits and Systems, 2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
J. Solid-State Circuits, 2017

2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
J. Solid-State Circuits, 2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
J. Solid-State Circuits, 2016

19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
J. Solid-State Circuits, 2015

High Frequency Buck Converter Design Using Time-Based Control Techniques.
J. Solid-State Circuits, 2015

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
J. Solid-State Circuits, 2015

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.
J. Solid-State Circuits, 2015

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links.
J. Solid-State Circuits, 2015

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS.
J. Solid-State Circuits, 2014

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
J. Solid-State Circuits, 2014

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques.
J. Solid-State Circuits, 2014

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
J. Solid-State Circuits, 2014

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014

A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
Proceedings of the Symposium on VLSI Circuits, 2014

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops.
J. Solid-State Circuits, 2013

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
J. Solid-State Circuits, 2012

A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control.
Proceedings of the Symposium on VLSI Circuits, 2012

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.
Proceedings of the Symposium on VLSI Circuits, 2012

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
J. Solid-State Circuits, 2011

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
J. Solid-State Circuits, 2011

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.
J. Solid-State Circuits, 2011

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
J. Solid-State Circuits, 2011

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2006
2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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