David Money Harris

Affiliations:
  • Harvey Mudd College, Claremont, CA, USA


According to our database1, David Money Harris authored at least 26 papers between 1994 and 2018.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2018
Evaluation of predictive technology models.
Microelectron. J., 2018

2017
MIPSfpga: using a commercial MIPS soft-core in computer architecture education.
IET Circuits Devices Syst., 2017

2015
Sequential Element Timing Parameter Definition Considering Clock Uncertainty.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
IEEE J. Solid State Circuits, 2013

Introductory digital design & computer architecture curriculum.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Implementation of a 64-bit Jackson adder.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Bubble Razor: An architecture-independent approach to timing-error detection and correction.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Yield-driven minimum energy CMOS cell design.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Implementation of 32-bit Ling and Jackson adders.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2008
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2008

Energy-delay tradeoffs in 32-bit static shifter designs.
Proceedings of the 26th International Conference on Computer Design, 2008

A MIPS R2000 implementation.
Proceedings of the 45th Design Automation Conference, 2008

2007
Parallelized radix-2 scalable Montgomery multiplier.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Parallelized radix-4 scalable montgomery multipliers.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

SE6 Secure Digital Systems.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Inexpensive Student-Assembled FPGA/Microcontroller Board.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Very High Radix Scalable Montgomery Multipliers.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

An Improved Unified Scalable Radix-2 Montgomery Multiplier.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2003
TestosterICs: A Low-Cost Functional Chip Tester.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

1999
A Counterflow Pipeline Experiment.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1994
The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers.
Proceedings of the Parallel Computer Routing and Communication, 1994

Architecture and implementation of the reliable router.
Proceedings of the Hot Interconnects II, 1994


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