Marek A. Perkowski
Orcid: 0000-0002-0358-1176Affiliations:
- Portland State University, OR, USA
According to our database1,
Marek A. Perkowski
authored at least 186 papers
between 1984 and 2023.
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Bibliography
2023
Comput. J., September, 2023
Quantum Inf. Process., January, 2023
Quantum Algorithms for Unate and Binate Covering Problems with Application to Finite State Machine Minimization.
FLAP, 2023
Discovering Emerging Applications of Multi-Valued Logic: Protocols for Human-Autonomy Teaming.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
2022
Inverse problems, constraint satisfaction, reversible logic, invertible logic and Grover quantum oracles for practical problems.
Sci. Comput. Program., 2022
Quantum Machine Learning, Logic Minimization, and Circuit Design by Optimizing Ternary-Input Binary-Output Kronecker Reed-Muller Forms.
FLAP, 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
2021
Binary, Multi-Valued and Quantum Board and Computer Games to Teach Synthesis of Classical and Quantum Logic Circuits.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Quantum Algorithm for Machine Learning and Circuit Design Based on Optimization of Ternary - Input, Binary-Output Kronecker-Reed-Muller Forms.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
A New Approach to Machine Learning Based on Functional Decomposition of Multi -Valued Functions.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the International Conference on Information and Digital Technologies, 2021
2020
Quantum-based algorithm and circuit design for bounded Knapsack optimization problem.
Quantum Inf. Comput., 2020
Quantum Inf. Comput., 2020
Int. J. Parallel Emergent Distributed Syst., 2020
A Polarity-based Approach for Optimization of Multivalued Quantum Multiplexers with Arbitrary Single-qubit Target Gates.
FLAP, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the Web Information Systems and Applications, 2020
2019
Theory Comput. Syst., 2019
Int. J. Unconv. Comput., 2019
Machine-learning based three-qubit gate for realization of a Toffoli gate with cQED-based transmon systems.
CoRR, 2019
A Reed Muller-based approach for optimization of general binary quantum multiplexers.
CoRR, 2019
Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA).
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
A Novel Machine Learning Algorithm to Reduce Prediction Error and Accelerate Learning Curve for Very Large Datasets.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
2018
A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Quantum Inf. Comput., 2018
Int. J. Soc. Robotics, 2018
Realization of Arithmetic Operators Based on Stochastic Number Frequency Signal Representation.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the Cloud Computing and Security - 4th International Conference, 2018
2017
Toward Improving Electrocardiogram (ECG) Biometric Verification using Mobile Sensors: A Two-Stage Classifier Approach.
Sensors, 2017
A General Data Mining Methodology Based on a Weighted Hierarchical Adaptive Voting Ensemble (WHAVE) Machine Learning Method.
J. Multiple Valued Log. Soft Comput., 2017
Memristor based 8-bit iterative full adder with space-time notation and sneak-path protection.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
ECG Biometric Identification Using Wavelet Analysis Coupled with Probabilistic Random Forest.
Proceedings of the 15th IEEE International Conference on Machine Learning and Applications, 2016
Quantum Machine Learning Based on Minimizing Kronecker-Reed-Muller Forms and Grover Search Algorithm with Hybrid Oracles.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Quantum Phase Estimation and Arbitrary Accuracy Iterative Phase Estimation Using Multivalued Logic.
J. Multiple Valued Log. Soft Comput., 2015
A Novel Weighted Hierarchical Adaptive Voting Ensemble Machine Learning Method for Breast Cancer Detection.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
Trans. Comput. Sci., 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
IEICE Trans. Inf. Syst., 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Logic synthesis and a generalized notation for memristor-realized material implication gates.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Int. J. Unconv. Comput., 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
2012
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?
J. Multiple Valued Log. Soft Comput., 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Using Formal Verification and Robotic Evolution Techniques to Find Contradictions in Laws Concerning Police Rules of Engagement.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
2011
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics
CoRR, 2011
Reversible Function Synthesis of Large Reversible Functions with No Ancillary Bits Using Covering Set Partitions.
Proceedings of the Eighth International Conference on Information Technology: New Generations, 2011
Improved Complexity of Quantum Oracles for Ternary Grover Algorithm for Graph Coloring.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Comparison of Influence of Two Data-Encoding Methods for Grover Algorithm on Quantum Costs.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Image Processing and Machine Learning for the Diagnosis of Melanoma Cancer.
Proceedings of the BIODEVICES 2011, 2011
2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Adaptive Selection of Intelligent Processing Modules and its Applications.
Proceedings of the 2010 International Conference on Artificial Intelligence, 2010
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Synthesis of quantum arrays with low quantum costs from Kronecker Functional Lattice Diagrams.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
Comparison of state assignment methods for "quantum circuit" model of permutative quantum state machines.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
Proceedings of the ISMVL 2009, 2009
Proceedings of the ISMVL 2009, 2009
2008
Erratum to: "Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition" [TCS 367 (3) (2006) 336-346].
Theor. Comput. Sci., 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the IEEE Congress on Evolutionary Computation, 2008
2007
J. Multiple Valued Log. Soft Comput., 2007
Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates.
J. Multiple Valued Log. Soft Comput., 2007
J. Syst. Archit., 2007
IET Comput. Digit. Tech., 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
2006
Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition.
Theor. Comput. Sci., 2006
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
J. Multiple Valued Log. Soft Comput., 2006
Proceedings of the Implementation and Application of Automata, 2006
Proceedings of the Theory and Applications of Models of Computation, 2006
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
2005
Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades.
J. Multiple Valued Log. Soft Comput., 2005
J. Multiple Valued Log. Soft Comput., 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 41th Design Automation Conference, 2004
Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Artif. Intell. Rev., 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 2003
2002
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts.
VLSI Design, 2002
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits.
VLSI Design, 2002
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs.
VLSI Design, 2002
Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture.
IEEE Micro, 2002
IEEE Micro, 2002
Logic Synthesis of Reversible Wave Cascades.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Reversible Logic Synthesis by Iterative Compositions.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002
2001
J. Syst. Archit., 2001
Labeled rough partitions - a new general purpose representation for multiple-valued functions and relations.
J. Syst. Archit., 2001
Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with Generalized Reed-Muller (AND-EXOR) forms.
J. Syst. Archit., 2001
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 2001 Congress on Evolutionary Computation, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Computers, 2000
Proceedings of the 2nd NASA / DoD Workshop on Evolvable Hardware (EH 2000), 2000
1999
Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
New compact representation of multiple-valued functions, relations, and non-deterministic state machines.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
Proceedings of the 24th EUROMICRO '98 Conference, 1998
An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures.
Proceedings of the 23rd EUROMICRO Conference '97, 1997
1996
Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Computers, 1996
1995
Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions.
VLSI Design, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
An Exact Solution to the Fitting Problem in the Application Specific State Machine Device.
J. Circuits Syst. Comput., 1994
A Filed Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping.
Proceedings of the Proceedings EURO-DAC'94, 1994
A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.
Proceedings of the 31st Conference on Design Automation, 1994
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
Proceedings of the 31st Conference on Design Automation, 1994
1993
Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
1992
Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines.
Proceedings of the Fifth International Conference on VLSI Design, 1992
The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs.
Proceedings of the Synthesis for Control Dominated Circuits, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992
A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping.
Proceedings of the conference on European design automation, 1992
Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions.
Proceedings of the conference on European design automation, 1992
Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks.
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
1990
Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Ovulo-computer: application of image processing and recognition to mucus ferning patterns.
Proceedings of the Third Annual IEEE Symposium on Computer-Based Medical Systems (CBMS'90), 1990
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
1988
A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
1984
Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler.
Proceedings of the 21st Design Automation Conference, 1984