Young-Hwa Kim

According to our database1, Young-Hwa Kim authored at least 8 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.
IEEE J. Solid State Circuits, 2020

2019
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

2013
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier.
IEEE J. Solid State Circuits, 2013

2012
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A time-domain flash ADC immune to voltage controlled delay line non-linearity.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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