Xiang Gao

Orcid: 0009-0002-8627-3247

Affiliations:
  • Zhejiang University, School of Micro-Nano Electronics, Hangzhou, China
  • University of Twente, Enschede, The Netherlands (PhD 2016)


According to our database1, Xiang Gao authored at least 15 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD.
IEEE J. Solid State Circuits, August, 2024

Analysis of Random Clock Jitter Effect in Time-Interleaved DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

+A 112Gbps DSP-Based PAM4 SerDes Receiver with a Wide Band Equalization Tuning AFE in 7nm FinFET.
Proceedings of the IEEE International Conference on Integrated Circuits, 2024

2022
A Flexible 0.73-15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique.
IEEE J. Solid State Circuits, 2021

20.2 A 3.09-to-4.04GHz Distributed-Boosting and Harmonic-Impedance-Expanding Multi-Core Oscillator with-138.9dBc/Hz at 1MHz Offset and 195.1dBc/Hz FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A calibration-free multi-phase sampling Type-II PLL.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A Calibration-Free Low Spur Multi-Phase Sampling PLL.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
Low Jitter and Low Power PLL:Towards The Utopia.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
Tutorials: Low-Jitter PLLs for wireless transceivers.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


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