Luns Tee

According to our database1, Luns Tee authored at least 9 papers between 1998 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2009
A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications.
IEEE J. Solid State Circuits, 2006

A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003
A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2001
A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers.
IEEE J. Solid State Circuits, 2001

1998
Recent developments in high integration multi-standard CMOS transceivers for personal communication systems.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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