Xianghong Hu

Orcid: 0000-0002-1237-4945

Affiliations:

Company of Chipeye Microelectronics Foshan Ltd., Foshan, China
Guangdong University of Technology, School of Integrated Circuits, School of Automation, Guangzhou, China

According to our database¹, Xianghong Hu authored at least 19 papers between 2019 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2025

A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2025

An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks.

[BibT_eX]

[DOI]

J. Syst. Archit., 2025

A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2025

2024

An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., December, 2024

2023

High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2023

A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

2022

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator.

[BibT_eX]

[DOI]

Microelectron. J., 2022

An efficient loop tiling framework for convolutional neural network inference accelerators.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2022

A high speed processor for elliptic curve cryptography over NIST prime field.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2022

SDQ: Stochastic Differentiable Quantization with Mixed Precision.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the HP3C 2022: 6th International Conference on High Performance Compilation, 2022

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Subgraph feature extraction based on multi-view dictionary learning for graph classification.

[BibT_eX]

[DOI]

Knowl. Based Syst., 2021

Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2021

2020

The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

A Resources-Efficient Configurable Accelerator for Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2019

Xianghong Hu

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