Bowen Wang

Orcid: 0000-0002-0173-7317

Affiliations:
  • Tsinghua University, Beijing, China


According to our database1, Bowen Wang authored at least 21 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A 0.1-1kbps, 9.4pJ/bit, Wake-Up Receiver with No-Standby-Clock and Level-Crossing Comparator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 2-18GHz Tunable Bandpass Filter with Dual-Path Transformer Technique for Ultra-wideband Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 65nm 8GHz E-PPWM/FSK IR-UWB Transceiver Achieving 2.4Gb/s Data Rate and 8.6pJ/b Energy Efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 0.07-mm<sup>2</sup> 32.7-kHz Frequency Reference with Aging Calibration Embedded 1-second Timer Scoring 22% Residual Error After 500-Hour Aging at 150°C in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 0.65V 10-to-21.5GHz Time-amplifying-based Sampling PLL Achieving 41.3-67.3fs jitter and -255dB Peak FoMT.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 1.6-to-16 GHz Sub-1-LSB INLpp 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
A Time-Domain Integration Comparison Scheme With Noise Immunity for Wake-Up Receivers.
IEEE Trans. Very Large Scale Integr. Syst., December, 2025

A Low-Noise Class-F<sub>23</sub> VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

An 8.1 dB SNR<sub>MIN</sub>, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

A 7.5-GHz Frequency-Hopping CDMA UWB Transceiver for Secure Multi-Sensor Connectivity.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fs<sub>rms</sub> Integrated Jitter and -98.5dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 1.8Gb/s 8GHz PSK-UWB Transceiver with Extended PPM/PWM Modulation and Embedded Carrier Spreading.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation.
IEEE J. Solid State Circuits, June, 2024

A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

2023
A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2020
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020


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